NVIDIA Careers Hiring ASIC Engineer – New College Graduate 2026

Physical Design Team

The Physical Design team at NVIDIA drives end-to-end chip implementation from RTL to GDS, including floor planning, PNR, timing closure, and physical verification. They collaborate closely with design teams to optimize performance, power, and area for GPUs and ASICs across multiple platforms.

What you’ll be doing:

• Work on all block/chip level PD activities.
• PD activities include floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
• Help team members in debugging tool/design related issues.
• Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
• Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.

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Timing Team:

The ASIC Physical Design (ASIC PD) team at NVIDIA designs and validates high-performance ASICs that power next-generation computing and AI platforms. The team works on large-scale integrated and chiplet-based silicon designs, delivering industry-leading performance, power efficiency, scalability, ultra-low latency, and maximum throughput, while ensuring robust timing closure and silicon reliability at advanced technology nodes.

What you will be doing:

• Own and drive full-chip and/or chiplet-level Static Timing Analysis (STA) from early design stages through final timing sign-off, ensuring robust timing closure.
• Lead timing convergence across multiple design partitions in a multi-mode, multi-corner (MMMC) environment, driving closure through effective cross-team collaboration.
• Contribute to top-level floorplanning, clock architecture definition, and timing budgeting, ensuring scalable and timing-aware design implementation.
• Define, review, and maintain comprehensive timing constraints (SDC) across functional and test modes to ensure accurate and efficient timing analysis.
• Collaborate closely with RTL, PnR, and DFT teams to identify and resolve timing bottlenecks while improving overall timing Quality of Results (QoR).
• Enhance and optimize timing analysis methodologies, sign-off flows, and automation in partnership with STA methodology teams to improve efficiency and scalability.
• Perform in-depth timing analysis across diverse operating scenarios and drive optimization strategies that balance performance, power, and reliability objectives.

Cognizant Off-Campus hiring for Analyst Trainee (Three-year full-time degree: 2024 or 2025 graduates)

DFX Team:

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry’s most complex semiconductor chips. This team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry’s most complex semiconductor chips.

What you’ll be doing:

• As a member of the DFT team, you will be working on verification of state of art Memory BIST logic along with other DFT circuits like JTAG, IO BIST and ATPG.
• You will be Validating test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools.
• Simulating Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign- off on Test coverage for various products using standard coverage metrics.
• Would work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix , and Memory-test productization.
• Partner closely with our design team to understand our architecture, then collaborating with QA engineers to deliver good test coverage and improve software quality.

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PSSG Team:

The PSSG (Applied Power Architecture) team at NVIDIA develops innovative power features and models to optimize chip performance across consumer, server, mobile, and automotive platforms. The team works on power estimation, silicon characterization, and calibration, ensuring accurate power measurement and alignment with architecture and design goals.

What you’ll be doing:

• Work with Arch, Design & validation teams to perform power bring up, characterize power saving & power management features
• Perform correlation of silicon KPIs with pre-si expectations.
• Work with HW and SW teams to optimize silicon power and perf/watt
• Create test plans and design experiments to accomplish goals identified for various studies
• Collect and analyze silicon power data to enable future chips’ power estimation models, design experiments to finalize modelling methods

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Circuit Design Team:

The Circuit Design (DIP) team at NVIDIA develops sophisticated cutting-edge digital IP, including advanced SRAM compilers, used across NVIDIA’s SoCs. They collaborate closely with system architects, design, validation, and product teams to deliver robust, scalable IP that powers next-generation semiconductor products to push the frontiers of AI innovation.

What you’ll be doing:

• Embedded SRAM design: Transistor-level circuit design and analysis, supervising layout implementation, physical and logical verification, timing analysis, power analysis, electromigration and post-silicon learning opportunity.
• SRAM compiler development: Envisioning, defining, and coding efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA’s extensive compute resources. Opportunity to use machine learning tools to solve circuit design challenges.
• Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.

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SOCD Team:

The SOCD team at NVIDIA builds and integrates sophisticated Tegra SoCs, collaborating across architecture, ASIC, physical design, CAD, DFT, and packaging teams. They work on putting the SOC top-level design together and developing scalable methodologies to enable efficient, next-generation SoC development.

What you’ll be doing:

• Drive SOC Assembly and design chip level functions for Tegra SOCs.
• Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.
• Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.
• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
• Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them

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CAD Team:

As part of the CAD team our engineers develop and support tools for all of NVIDIA’s semiconductor products. In addition, they also develop in-house tools in Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL.

What you will be doing:

• Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object-oriented techniques.
• Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs.
• Support development of tools using C++/Python/TCL.
• Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks.

What we need to see:

• Pursuing B.Tech./ M.Tech
• Strong analytical skills to solve difficult problems
• Understanding of programming languages and processor
• Good grasp of operating system fundamentals & digital design concepts
• Strong debugging, problem-solving, and communication skills; ability to work in teams

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